Objective 1 Distinguish between true and false statements concerning the terms which relate to Part 2 in the index for this block, or explain the terms in your own words.
Objective 2 Form the 2's complement of a given binary number.
The complement of a number has all the 1s changed to 0s and all the 0s changed to 1s. The 2's complement is found by first finding the complement then adding 1. The additive inverse is another name for the 2's complement.
SAQ2 a) Write down the complement of 1010 0101 0101 1010
b) Find the 2's complement of the signed integer 1011 0111. 0100 1000 + 1 = 0100 1001
c) Find the additive inverse of the signed integer 0000 1111. 1111 0000 + 1 = 1111 0001
Objective 3 Add two binary integers; add and subtract two 8-bits 2's complement numbers; outline how to proceed for larger 2's complement integers.
Binary digits are added according to the following rules:
| 0 + 0 = 0 |
| 0 + 1 = 1 |
| 1 + 1 = 10, which is 0 and carry 1 |
| 1 + 1 + 1 = 11. which is 1 and carry 1 |
SAQ1 a) Add the 4-bit binary numbers 1011 and 0011. Check your result by converting all numbers to denary.
b) Add the 8-bit binary numbers 0110 1100 and 0001 0110
SAQ3 Peform the specified calculations on the following 2's complement numbers.
a) 1011 1111 + 1101 1100 The result is (1) 1001 1011. The extra 1 can be ignored as two negative numbers are being added.
b) 1100 1010 - 0000 1110 The calculation is converted into an addition by finding the inverse additive of the number to be subtracted. This is 1111 0001 + 1 = 1111 0010. So the calculation is 1100 1010 + 1111 0010 = (1) 1011 1100. Again the inth bit can be ignored.
SAQ4 Carry out the following additions of 2's complement integers and state in each case whether 2's complement overflow has occurred.
a) 1111 1111 + 1100 0000 1111 1111 + 1100 0000 = (1) 1011 1111 The sign bit has not been altered, and so 2's complement overflow has not occurred.
b) 0101 1111 + 0101 0000 0101 1111 + 0101 0000 = 1010 1111. 2's complement overflow has occurred because the sign bit indicates a negative number while the addition of two positive numbers should give a positive result.
c) 1101 1100 + 1000 0000 1101 1100 + 1000 0000 = (1) 0101 1100. 2's complement overflow has occurred because the sign bit indicates a positive number while the addition of two negative numbers should give a negative result.
d) 0101 1111 + 1011 1111 0101 1111 + 1011 1111 = (1) 0001 1110. 2's complement overflow has not occurred since the numbers to be added have opposite signs.
Objective 4 Recognize when overflow has occurred in arithmetic using 2's complement numbers.
In the case of 2's complement integers, overflow has ocurred if the sign bit is interfered with in the result.
SAQ5 a) Without carrying out the subtractions, identify those subtractions of 2's complement integers where 2's complement overflow could possibly occur.
i) 1011 1011 - 1001 1100 ; ii) 1011 0000 - 0101 0000 ; iii) 0101 1101 - 0111 1011 ; iv) 0111 1000 - 1011 1010
Only in cases ii) and iv) could 2's complement overflow occur because the sign bits are positive and negative or negative and positive.
b) Carry out the subtraction (by complementing and adding) in those cases where overflow could occur and hence state whether 2's complement overflow has occurred.
Objective 5 Perform (bitwise) AND, OR and XOR operations on a pair of binary words and NOT operations on a single binary word.
| NOT (complement) | changes all the 1s in a binary word to 0s and vice versa |
| AND | the result is 1 only if both digits are 1 |
| OR | the result is 1 if either or both digits are 1 |
| XOR | the result is 1 if either digit is one, but not both |
SAQ 6 a) If A = 0011 0111 and B = 0100 1011 find
i) NOT A - NOT is the complement of A, which 1100 1000
ii) A AND B - 0011 0111 AND 0100 1011 = 0000 0011, so A AND B = 0000 0011
iii) A OR B - 0011 0111 OR 0100 1011 = 0111 1111 so A OR B = 0111 1111
iv) A XOR B - 0011 0111 XOR 0100 1011 = 0111 1100 so A XOR B is 0111 1100
b) i) Is A AND B = B AND A? Yes
ii) Is A OR B = B OR A? Yes
iii) Is A XOR B = B XOR A? Yes
Objective 6 Classify computer instructions as data move, arithmetic/logic or control.
| Examples of data move instructions | load and store instructions |
| Examples of arithmetic / logic instructions | add, subtract and AND instructions |
| Examples of control instructions | Unconditional jump or conditional jump |
SAQ7 Classify the following five instructions as arithmetic/logic, data move or control.
a) Jump back six instructions - control
b) Subtract the number held in a particular memory location from the number held in one of the processor's registers. - arithmetic / logic
c) Output the number held in one of the processor's registers to the printer. - data move
d) Read a data word held in a particular memory location and copy it inot one of the processor's registers. - data move
e) Test if the number in one of the processor's registers is zero, and if it is, jump forward four instructions. - control
Objective 7 Explain the purpose of the following microprocessor components: arithmetic-logic unit, control unit, accumulator, instruction pointer, stack pointer, flag register, index register, general-purpose registers.
SAQ8 The literature for a particular microprocessor describes it as having four registers, which it calls A, B, C and PC. At first sight, what would you assume to be: Suggest how each of these registers would be used during execution of a program.
a) the accumulator
A. The accumulator is used to hold data which has been read in from memory or is to be written to memory, to hold data which is to be operated on in the ALU and to hold results of arithmetic or logic operations in the ALU.
b) the instruction pointer
PC (an alternative name for the instruction pointer is program counter). The content of this register is the address of the location holding the next instruction to be executed.
c) general-purpose register
B and C. These reigsters are used in much the same way as the accumulator. Their use reduces the extent to which interim results that are required during program execution have to be transferred to and from memory.
Objective 8 Given hex op-codes, write short sequences of machine instructions to perform a specified small task.
Machine instructions consist of two parts, an op-code and an operand. The length of each instruction in a particular microprocessor's instruction set varies, but is generally an integer number of words.
SAQ9 Write a sequence of hex machine instructions to subtract 1 from the contents of the memory location with hex address 0100 and store the result in the memory location with hex address 0180. Assume that the microprocessor has an instruction with op-code 81E8 whose effect is to subtract the number specified as the operand from the contents of the accumulator and then place the result in the accumulator.
The sequence is
| op-code | operand |
| A100 | 0100 |
| 81E8 | 0001 |
| A300 | 0180 |
The first instruction reads the number into the accumulator from the memory location with hex address 0100. The next subtracts 1 from the accumulator's contents. The last stores the accumulator's contents in the memory location with hex address 0180.
Objective 9 State the effect of the following computer instructions: load, store, add, subtract, AND, jump, jump if zero, jump if negative, call, return, copy register.
Objective 10 Explain the following addressing modes and apply them to the relevant instructions from objective 9 above: immediate, direct, relative, indexed, register-reference.
SAQs for objectives 9 & 10
SAQ10 a) What exactly is the difference in the overall effects of load the accumulator instruction in immediate addressing mode and a load the accumulator instruction in direct addressing mode, if in both cases the operand of the accumulator is hex 0500?
In immediate addressing mode the hex value 0500 is placed in the accumulator. In direct addressing mode the contents of the location whose hex address is 0500 are placed in the accumulator.
b) Is it theoretically possible to have such an entry as the following? If possible, what would be the effect of the instruction?
i) an add instruction with direct addressing - Yes. the number to be added would be the one hled in the location whose address was given as the operand of the add direct instruction.
ii) a store instruction with immediate addressing - No. The store instruction must include an address in order for the microprocessor to know where in memory to store the data from the accumulator.
SAQ11 a) If a microprocessor has a second general-purpose register, called register B, what would be the effect of an add direct to register B instruction if the operand of this instruction is hex 0500?
The number stored in location with hex address 0500 will be added to the contents of register B, and the result will be stored in register B.
b) Explain why the op-code of this instruction would necessarily be different from the op-code of the microprocessor's add direct to accumulator instruction.
The op-code is the part of the instruction that specifies what operation is to be carried out. If the operation differs in any detail from some other operation then it must have a different op-code.
c) Would the microprocessor's add immediate to register B instruction have a different op-code from its add direct to register B instruction?
Yes; because the operations of the two instructions differ they must have different op-codes.
SAQ12 In a particular microprocessor at a particular point in a program the accumulator holds hex 0001 and register B also holds hex 0001. The memory location with hex address 0300 holds hex FFFF.
a) What will be in the accumulator after the microprocessor has executed an instruction whose op-code corresponds to AND immediate with the accumulator and whose operand is hex 0300?
The AND operation is carried out between the operand, hex 0300, and the contents of the accumulator, hex 0001. The result is hex 0000.
b) What will be in register B after the microprocessor has executed the instruction whose op-code corresponds to AND direct with register B and whose operand is hex 0300?
This is an instruction in direct-addressing mode, so one of the data words involved in the AND operation is the one stored in the location with hex address 0300, which is FFFF. The other is in register B and so is hex 0001. The result is hex 0001.
SAQ13 In a particular microprocessor the hex op-code of an unconditional jump relative instruction is EB00.
a) What is the effect of the hex machine instruction EB00 0009 if the instruction pointer holds hex 0300?
This is a jump relative instruction with hex operand 0009. Therefore 9 is added tothe instruction pointer's contents, resulting in hex 309.
b) What is the effect of the hex machine instruction EB00 FFF0 if the instruction pointer holds hex 0510?
Here hex FFF0 is added to the instruction pointer's contents, which is equivalent to denary 16 or hex 10 being subtracted from them. The result is hex 0500.
SAQ14 A particular microprocessor has a subtract immediate from accumulator instruction whose hex op-code is 81E8 and a jump relative if preceding result zero instruction whose hex op-code is 7400. The two hex machine instructions
| op-code | operand |
| 81E8 | 0001 |
| 7400 | FFFA |
are to be executed. In which, if any, of the following cases will the instruction pointer's contents be reduced by 6?
a) The accumulator initially holds hex 0002; b) The accumulator initially holds hex FFF; c) The accumulator initially holds hex 0001
Only in case (c) will the subtract instruction cause the accumulator's contents to become zero. So only in case (c) will the jump be carried out. Since adding hex FFFA is equivalent to subtracting denary 6, only in this case will the instruction pointer's contents be reduced by 6.
SAQ20 The table shows contents of a portion of main memory. If the accumulator holds hex 1039, register B holds hex 0005 and the index register holds hex 0002.
| address | contents |
| 0800 | A000 |
| 0801 | 0F19 |
| 0802 | 0007 |
| 0803 | A051 |
| 0804 | F1EA |
| 0805 | D315 |
| 0806 | B096 |
a) What happens if load indexed A 0801 is executed? The contents of the location with hex address 0801 + 0002 = 0803 are loaded. So hex A051 is loaded into the accumulator.
b) What happens if store indexed B 0804 is executed? The contents of register are stored in the location with hex address 0804 + 0002 = 0806. So the contents of the location with hex address 0806 become equal to hex 0005.
c) What happens if subtract indexed B 0800 is executed? The number to be subtracted is found in the location with hex address 0800 + 0002 = 0802. So hex 0007 is subtracted from register B's contents (0005) to give the result of FFFE which is placed in register B.
Objective 11 Select suitable computer instructions in suitable addressing modes to perform specified small tasks.
SAQ16 Write down the computer instruction which carries out the step: "Set the contents of the counter register to 10." Assume that a second general-purpose register, register B, is available for the counter register and that it can be briefly referred to as B.
load immediate B 000A
SAQ17 Write down the instruction which carries out the step "Subtract 1 from the contents of counter".
subtract immediate B 0001
SAQ21 A particular program needs to multiply the number in the accumulator by 50. A subroutine to perform this task is held in a set of memory locations starting at the one with hex address 0A00.
a) What computer instruction will cause this subroutine to be executed? call direct 0A00
b) What other information is needed about the behaviour of the subroutine before it can successfully be incorporated in a main program?
You need to know where the result of the multiplication is stored at the end of the subroutine. It is also necessary to know what registers are used by the subroutine to hold temporary results.
Objective 12 Determine the contents of a short section of main memory containing a low-level program segment, given the op-codes of the instruction set.
Objective 13 Detect and correct errors in short lists of computer instructions which are intended to perform a specified task.
Objective 14 Explain why subroutines are useful in low-level programming and state what happens to the stack and stack pointer during subroutine calls and return instructions.
SAQ22 What is the complete list, in order, of microprocessor actions when a return from subroutine instruction is executed?
| 1 | Copy into the instruction pointer the data word stored in the location pointed to by the stack pointer |
| 2 | Incremement the stack pointer's contents |
SAQ23 A program with several subroutines, some of which are nested, is being executed. Call and return instructions occur in the following order:
| call direct | 0A00 |
| call direct | 0C80 |
| call direct | 0DD0 |
| return | |
| return | |
| call direct | 0D80 |
| return | |
| return |
The contents of the stack pointer are intially hex 0EFF.
i) What will be the contents of the stack pointer after the first call instruction has been executed? Hex 0EEE
ii) Where will each of the four return addresses be stored? The first will be stored in the location with hex address 0EEE. The second in 0EED. The third in 0EEC. By the time the fourth call is executed, two return addresses have already been retirieved, so it will be stored in 0EED.
iii) What will be the contents of the stack pointer after all of the call and return instructions in the above list have been executed? It will be 0EEF, just asit was before any call or return instructions had been executed.
Objective 15 Indicate in general terms what happens during the fetch-execute sequence for an instruction; given a simple microprocessor architecture and the list of steps of a particular instruction's execute sequence, recognize which instruction it is, or amend, complete or correct a list so that it corresponds to a particuar instruction.
| The fetch sequence | |
| 1 | The instruction pointer's contents are copied onto the address bus |
| 2 | A read operation is performed in main memory, which places the contents of the addressed location on the data bus |
| 3 | The data on the data bus is copied into the op-code register |
| 4 | The instruction pointer's contents are incremented by 1 |
| The execute sequence | if it's a one word instruction |
| 1 | the steps appropriate to the instruction are carried out |
| The execute sequence | if it's a two word instruction |
| 1 | the instruction pointer's contents are used to locate the operand of the instruction in memory, the oeprand is read and copied into the Temporary Address Register or Temporary Data register, as appropriate |
| 2 | the instruction pointer's contents are incremented by 1 to point to the next instruction |
| 3 | the steps appropriate to the instruction are carried out |
SAQ24 The steps of the execute sequence of the load direct the accumulator instruction are given below. Which steps would not be needed if the execute sequence was instead for a load immediate the accumulator instruction?
| 1 | The instruction pointer's contents are placed on the address bus |
| 2 | A read operation in memory places the contents of the addressed location on the data bus |
| 3 | The data on the data bus is copied into the temporary address register |
| 4 | The temporary address register's contents are placed on the address bus |
| 5 | A read operation in memory places the contents of the addressed location on the data bus |
| 6 | The data on the data bus is copied into the accumulator |
| 7 | The instruction pointer's contents are incremented by 1 |
Steps 3 to 5 inclusive must be omitted. Then the operand of the instruction is copied straight into the accumulator, which is what is required for a load immediate the accumulator instruction.
SAQ25 The execute sequence for an instruction drawn from the instruction set of the microprocessor of Figure 19 is as follows. Which instruction is this?
| 1 | The instruction pointer's contents are placed on the address bus |
| 2 | A read operation in memory places the contents of the addressed location on the data bus |
| 3 | The data on the data bus is copied into the temporary address register |
| 4 | The temporary address register's contents are placed on the address bus |
| 5 | A read operation in memory places the contents of the addressed location on the data bus |
| 6 | The data on the data bus is copied into the temporary data register |
| 7 | The contents of the accumulator pass to one input of the ALU and the contents of the temporary data register pass to the other input |
| 8 | The control unit signals the ALU to subtract and the result appears on the data bus at the ALU's input. |
| 9 | The data on the data bus is copied into the accumulator. |
| 10 | The instruction pointer's contents are incremented by 1 |
This is the execute sequence for a subtract direct from the accumulator instruction.
| You are not expected to memorise the steps of any fetch-execute sequence for yourself. You should, however, be able to answer questions similar to SAQs 24/25 given a simple processor architecture. |