Objective 1 Distinguish between true and false statements concerning the terms which relate to Part 2 in the index for this block, or explain the terms in your own words.
Objective 2 State and briefly describe the primary goals of an ideal data-transfer mechanism.
The characterstics of an idea data-transfer technique are:
| timely response | should be completed asap |
| regulated transfers | need to negotiate and agree the transfer |
| error-free transfers | don't increase the possibility of errors |
| minimal processor overhead | don't get the processor bogged down |
| multiple interfaces | handle simultaneous requests |
| prioritised requests | fast peripherals before slow peripherals |
Objective 3 Explain the pacing, polling, interrupt and DMA data-transfer techniques, giving the advantages and disadvantages of each one relative to the other techniques
Pacing is a transfer technique which is initiated and controlled by the processor. A common example of pacing is processor-to-main memory transfers. packing for inputer isnot very successful. Pacing for output is often used in simple systems because of its simplicity, both in hardware and software.
Polling is a transfer technique which is initiated by the processor but controlled by the device. Polling has the advantage over pacing of ensuring data is not lost. However, this technique does not improve the efficiency of the transfer. It can also lead to the processor gettingstuck in an endless loop is the device develops a fault. The solution is to incorporate a counter into the wait loop so that an exit from the loop will always happen.
Interrupts are a data transfer method by which the device initiates the transfer, but the actual transfer is controlled by the processor. Interrupts can prioritise requests.
DMA transfers are device initiated and device controlled. With DMA transfers, data passes directly between the device and main memory. This is faster than if the processor were involved.
Objective 4 Work out the required pacing delay and the efficiency of transfer for a given pacing example.
SAQ1
Objective 5 For a given example decide on a suitable data-transfer technique, and outline the essential components of an interrupt service routine.
SAQ2
Objective 6 Describe how an individual status flag can be isolated from other status flags by masking and use the masking technique in a given example
SAQ3
Objective 7 Describe generally the operation of hardware and software handshaking, giving examples where handshaking techniques might be available.
Handshaking is where data is transferred using a defined sequence of two-way control signals. Both the parallel and serial ports of IBM-PC compatible computers have such hardware handshaking signals.
Sometimes additional connections are not available, so hardware handshaking cannot be used. In these cases, software handshaking can be used where special data words are sent by the device to indicate when it is ready to recieve data or notable to take any more data. Another method of software handshaking involves sending blocks of data. Each block is acknowledge dby the reciever, and if a block is received incorrectly, it can be sent again.
SAQ4
SAQ5
Objective 8 Outline the principles of block-transfer protocols and apply them to questions about a specific block-transfer protocol
A software handshaking technique splits the data into blocks and then forms it into packets. Each packet contains the data, and information about the packet length, type and identity and also contains a check word. If a packet is received correctly the receiver returns an acknowledge packet. If an error is detected, a not-acknowledge packet is returned which indicates to the transmitter that re-transmission of the packet is required.
SAQ6
Objective 9 Describe the sequences of events occurring following an interrupt and outline the essentail components of an interrupt service routine.
When an interrupt is recognised by the processor, the following happens:
| processor stops execution of its current program | |
| processor saves the contents of its instruction pointer and possibly other register contents | |
| processor execute an interrupt service routine | |
| once this routine is complete, the contents of the instruction pointer and any other registers are restored and execution of the program continues |
Objective 10 Describe the various methods of determining the source of an interrupt giving each method's advantages and disadvantages over other methods.
To cater for multiple peripherals, some processors incorporate a number of interrupt inputs and each device is allocated its own separate interrupt.
If a number of interrupts have to use a single interrupt input the processor can determine the source of the interrupt by executing a skip chain or by using a hardware approach called daisy chaining.
A skip chain consists of the processor testing each device's status flag to determine the source of the interrupt. Priority can be achieved by ordering the testing of the status flags.
Daisy chaining involves a special interrupt acknowledge signal being passed through each device interface. The interface whose device caused the interrupt responds by putting a special device code on the processor's data bus. This code is used by the processor to determine the start of the address of the device's service routine by the use of an interrupt vector table. Priorities can be achieved by the order in which the interrupt acknowledge signal is fed through the peripheral interfaces.
SAQ7
Objective 11 For a given example decide, giving reasons, whether a software (skip chain) or hardware (daisy chain) approach might be the more suitable method of determining the source of interrupts
Objective 12 Outline the structure, essential components and operation of an integrated interrupt controller
An intergrated interrupt controller is one such as the Intel 8529A PIC (programmable interrupt controller). This device can handle interrupts from up to 8 devices. The device has registers that allow each device's interrupt to be masked, that indicate which devide is currently being serviced and which devices are awaiting service. Priorities are achieved by a particular connection of the devices to the various interrupt inputs. PICs can also be cascaded to allow interrupts from more devices.
SAQ8
Objective 13 For a given example suggest, giving reasons, an appropriate priority order for the various interrupting devices.
Objective 14 Explain interrupt nesting and its advantages and describe the additional interrupt masking and enabling functions that must be performed in the various interrupt service routines to implement interrupt nesting
The ability to mask devices' interrupts signals allows the service routines for each device to permit high-priority devices to interrupt their service routines, but not lower-priority devices. This is called interrupt nesting.
SAQ9
SAQ10
Objective 15 Describe non-maskable interrupts and the reason for their inclusion. Suggest uses for such processor inputs.
For very important interrupts such as an impending power failure, processors usually include a separate interrupt input which cannot be masked - known as a non-maskable interrupt.
Objective 16 Outline the components and operation of each component of a serial-interface device driver
A UART device which is used in serial transfers usually separate the transmit and receive sections, thus allowing them to be treated separately. An interrupt-based program module to control a UART is called a device driver and may be split into two parts. The first provides the initialisationof the UART and interrupt system and the second is the actual interrupt service routine.
SAQ11
SAQ12
Objective 17 Describe the components and operation of a FIFO buffer giving examples of when such buffers might be used.
A FIFO buffer is a section of memory that is shared between the main program and the interrupt service routine. Implementing such aa buffer requires the use of an IN and OUT pointer and some method of indicating when the buffer is full or empty - either by comparing the values of the pointers or by the use of software flags.
SAQ13
Objective 18 Explain the software interrupts and their uses, with particular reference to the IBM PC
Software interrupts are special processor instructions that have the same effect as a hardware interrupt. Such instructions are commonly used to allow programs access to device drivers without the program having to know the exact location of these drivers. E.g. ROM-BIOS routines in IBM-PC.
Objective 19 List the components of a DMA controller and describe the operations occurring at each stage in a complete DMA transfer
The components of a DMA controller are the address register (to hold the address of memory that the data will go to); the word counter (to count how many data words have been transmitted); the device selector and controller (to control the flow of data) and the device controller (to control the control bus)
Objective 20 Outline how DMA was used in the original IBM PC
| 1 | used an integrated interrupt controller, the Intel 8237 chip, which can support DMA with up to 4 different devices |
| 2 | data could be transferred singly or in blocks (blocks are faster but effectively halt the processor) |
| 3 | DMA was used for floppy and hard disk transfers as well as for memory refreshing og the dynamic RAM section of main memory |
Objective 21 Outline how bus mastering is used in Windows-based computers
Bus mastering is a high-speed data transfer technique between interfaces or between an interface and main memory.