Objective 1 Distinguish between true and false statements concerning the terms which relate to Part 3 in the index for this block, or explain the terms in your own words.
Objective 2 State why there is a drive for greater computer and processor performance.
The drive for increased performance is driven by the requirements of more sophisticated software. Enhancements in the technology of integrated-circuit fabrication have enabled faster microprocessors to be manufactured but his alone has not satisfied the requirements for increased performance.
Peformance can be measured in MIPS (Millions of Instructions per Second) and FLOPS (Floating Point Operations per second). Also, benchmark programs can be run.
Objective 3 Give the causes for bottlenecks in the traditional von Neumann architecture and state whether particular features of newer architectures are likely to alleviate or exacerbate the bottleneck.
The two essential features of the Von Neumann model are:
| 1 | that the computer processes data sequentially |
| 2 | that the program defining the sequential processing is stored in the computer's main memory |
The Von Neumann architecture has a single processor with a single arithmetic-logic unit (to carry out sequential processing) and a single main memory (to hold the program and the data which the program manipulates). The two are linked by an address bus, a data bus and a control bus.
The causes for bottlenecks are: 1) carrying out sequential processing using a single ALU limits the speed of the computer; 2) so much data is transferred in both directions between the processor and main memory that the data bus connecting them can become a bottleneck.
SAQ2 Think carefully about how (and when) instructions and data move between main memory and cache memories. Are there any circumstances in which an instruction cache and a data cache can relieve the problem of the bus bottleneck? Are there any circumstances where they can exacerbate it?
Instructions and/or data have to be copied from the main memory back to the cache memories in the first place. Updated data may have to be copied back from the data cache at some stage. These operations use the data bus and so have the potential to exacerbate the bus bottleneck, not relieve it, unless the control unit is able to schedule this copying at times when the data bus is not otherwise being used.
An instruction cache does relieve the bottleneck during a loop in that it saves all the instructions from a lopp being repeatedly read from main momery while the loop is being executed.
A data cache will relieve the bus bottleneck if items in a block of data are each being used several times.
At the end of a loop or a block of data the cahce memories need to be filled with new instructions or data to correspond with the next part of the program. Copying these instructions could well exacerabte the bus bottleneck.
SAQ3 What effect is the incorporation of a floating-point unit on the chip likely to have on the problem of the bottleneck?
It's likely to exacerbate the bus bottleneck because both the floating-point unit and the main execution unit may be performing memory read and write operations, rather than just the main execution unit. So the demands on the data bus will be greater.
SAQ4 Is the instruction prefetch likely to alleviate the problem of the bottleneck, or to exacerbate it?
It can alleviate the bottleneck because the execute sequence of some instructions (e.g. load, store) includes memory access while that of others (e.g. add register, copy register) does not. Instruction prefetch allows the control unit to use periods when the data bus would otherwise be idle to read in the op-code and operand of the next instruction(s) thus smoothing out the activity on the bus and reducing the possibility of bottlenecks.
SAQ6 Which features of RISC processors tend to exacerbate the bus bottleneck problem? Which alleviate it?
To alleviate the bottleneck:
To exacerbate the bottleneck:
Objective 4 Describe how improved IC fabrication technology is enabling greater processor performance.
Features can be incorporated onto the chip itself which enable the processor to execute a program faster. Sometimes these features involve the processor doing more than one thing at once. E.g. cache memories, floating-point units, instruction prefetch.
Objective 5 Explain the advantages of cache memory and outline the use of instruction and data caches.
Access to cache memory is very fast because there is no need to send signals to another chip and so the slow data transfer rates of the address and data buses can be avoided. Also, the read and write speeds of the on-chip memory can be made much closer to the clock rate of the microprocessor than can speeds for separate memory chips.
An instruction cache is used to store instructions from the program the processor is executing andisuseful when the processor is executing a loop.
A data cache just holds data and is useful when the processor is working on a block of data.
Objective 6 Explain the advantages of instruction prefetch and outline the use of an instruction queue.
Another way in which a microprocessor can be made to execute instructions faster is for it to incorporate an instruction queue where instructions are held ahead of being executed (when the processor has nothing else to do).This means that the processor is presented with the next instruction as soon as it has finished the previous one, without a pause while the next instruction is retrieved.
Collecting an instruction ahead of time is called instruction prefetch. The advantages are that instructions are executed faster as the temporary registers that hold the prefetched instructions can be within the processor itself and so able to output directly on to the internal data paths of the processor.
Objective 7 Explain the advantages of instruction pipelining and describe its operation.
In an instruction pipeline, each instruction is divided into several discrete sections and then instruction execution is overlapped so that the first section of the second instruction is being executed at the same time as the second section of the first instruction. This increases performance because the overall effect is as if one instruction were being executed in every cycle (rather than taking four cycles).
This does however exacerbate the bottleneck because instructions have to be sent to the processor every cycle rather than one every few cycles.
Objective 8 State and briefly explain the principles of RISC microprocessors; compare features of RISC and CISC microprocessors; indicate to what extent a particular microprocessor exhibits the features of a RISC microprocessor.
RISC = Reduced Instruction Set Computer. It is based around the findings that processors spend around 80% of their time executing around 20% of the instructions in the instruction set. The features of a RISC processor are:
CISC = Complex Instruction Set Computer. It has a larger and more complex instruction set and therefore has a lower MIPS speed than a RISC processor. However a CISC processor has less instructions per task than a RISC.
SAQ12 What features of the PowerPC 601 are consistent with the description of the RISC microprocessors given in Section 2.6.2? Are there any features which are not consistent?
The PowerPC exhibits the following features of a RISC microprocessor:
There are no RISC features that that PowerPC does not share.
Objective 9 State the effect of the following computer instructions: OR, XOR, jump if carry, jump if overflow, increment, decrement, clear, push register, pop register, in, out.
Objective 10 Explain the following addressing modes and apply them to the relevant instructions: register indirect, base, base-indexed.
SAQ7 In a 16-bit microprocessor with three general-purpose registers, register C holds hex2000 and register B holds hex 2001. The instruction
load indirect register BviaC
is executed. The contents of the relevant are of memory area:
| address | contents |
| 1FFF | 2379 |
| 2000 | 1F01 |
| 2001 | E670 |
| 2002 | A2BC |
a) Which register's contents will change?
The contents of register B
b) What will they change to?
They will change to the contents of the location with hex address 2000, which are hex 1F01.
SAQ9 In a microprocessor which ofers base-indexed addressing, the base register holds hex 4000 and the index register holds hex 0007. Where will the accumulator's contents be stored when the microprocessor executes the following instructions?
store base-indexed A 0200
Hex 4000, 0007 and 0200 are added to form the address of the destination of the accumulator's contents. Hence these contents will be stored in the locations with hex address 4207.
Objective 11 Explain why 1-word instructions can be preferable to longer instructions.
Objective 12 Outline how memory is implemented in commercial microprocessor systems.
Unlike the simulated microprocessor system, all commercial microporcessor systems in general-purpose computers need to be able to access individual bytes of data. Each location in memory therefore holds 1 byte (8 bits). In a 32-bit system, instructions and data words are stored in groups of four memory locations, and the circuitry and memory chips are arranged in a way that facilitates this process.
SAQ10 How many memory chips must be arranged side by side in a) a 16-bit system b) a 64-bit system. What would be the byte addresses on chip M0 in each case?
a) In this case, two memory chips are needed. Chip M0 will have byte addresses 0, 2, 4, 6, 8, etc.
b) Eight memory chips are needed. Chip M0 will have byte addresses 0, 8, 16, 24, 32 etc.
Objective 13 Outline the principles whereby special registers can be used to form a long address from shorter data words (as with the 8086's segment registers).
Objective 14 Briefly outline the enhancements that have taken place in the Intel 8086 series since its introduction in 1978.
SAQ11 Summarise as many differences as youcan from the above descriptions between the original Intel 8086 and a Pentium II microprocessor.
| Intel 8086 | Pentium II | |
| Word length | 16 bits | 32 bits, with a 64-bit data bus |
| Cache memory | No | 16K bytes each of data and instruction cache |
| On-chip floating-point unit | No | Yes |
| Other simultaneious on-chip operations | Instruction prefetch; bus interface unit could calculate address while execution unit carried out other tasks | Instruction prefetch; pipelining; two integer execution units |
| Other | No support for multitasking | Support for multitasking |
| Completely microcoded | A few instructions hardwired |
Objective 15 With reference to written descriptions of the two microprocessors, make brief comparisons between a specified member of the Intel 8086 series and a specified member of the PowerPC series.
SAQ13 Briefly compare the Intel Pentium and the PowerPC 601 under the following headings: word length, addressing modes, instruction set, on-chip cache memory, on-chip floating-point unit, extent to which they are superscalar.
| Intel Pentium | PowerPC 601 | |
| Word length | 32 bit, but with 64-bit data bus | 32 bit, but with 64-bit data bus |
| Addressing modes | Relatively many, with access to memory allowed for many types of instruction | Relatively few, with access to memory allowed only for load and store instructions |
| Instruction set | Complex, with instructions of different lengths | Simple, with all instructions of a fixed length |
| On-chip cache memory | 8K bytes of instruction cache and 8K bytes of data cache | 32K bytes |
| On-chip floating-point unit | Yes | Yes |
| Superscalar | Up to two instructions per clock cycle to the integers units | Up to three instructions per cycle: one each to the integer unit, the floating-point unit and the branch processing unit |
Objective 16 Given written descriptions of two microprocessors, make a brief comparison of these microprocessors.